John R Tucker

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John R Tucker
268 Engineering Sciences Building
217.333.4810
jrtucker@illinois.edu

ICMT Faculty

Research Interests:

  • New nanoelectronic architectures in silicon.
  • Center for Silicon Quantum Computers (Director).
  • Metal silicide source/drain MOS transistors scaled to ~10nm gate length.
  • Atom-scale devices made by STM P donor patterning and silicon overgrowth.

Description of Current Research

For the last ten years, my research has focused on developing a new silicon-based technology that can go beyond the limits of CMOS. My colleague, T.-C. Shen, and I have shown that delta-layer doping can be patterned with atomic resolution. Epitaxial P-donor nanowires of ~10-100nm width have been grown into the silicon crystal between implanted contacts. Their transport properties are accurately described by previous theories for ultra-thin metal films. Our long-term goal is to combine these nanowire doping patterns with Si/SiGe quantum wells to realize 3D ultra-low-power epitaxial integrated circuits that could eventually support biological and quantum functionality.

News About Our Research

This year, we obtained a UV excimer laser for H-desorption experiments on the hydrogen terminated silicon surface. The goal here will be a practical lithography for delta-layer patterning, similar to the sources used for CMOS processing. STM lithography would then be used only for atom-scale features. A large manuscript has been drafted recently to describe this approach to silicon-based electronics and its possibilities.

Honors and awards

  • IEEE Microwave Pioneer Award 2002 "for generalizing microwave mixer theory to include photon-assisted tunneling, and discovering new effects leading to quantum-noise-limited millimeter wave receivers."
  • Fellow, American Physical Society 2002
  • Visiting Professor, Technical University of Delft, 1999.
  • NRC Senior Fellow, NASA Institute for Space Studies, New York, 1980.
  • Eta Kappa Nu Faculty Initiate (for excellence in teaching), Fall 1995
  • NSF Fellow, Harvard University - 1967 to 1971
  • President, Caltech Chapter of Tau Beta Pi - 1965
  • Developed the quantum generalization of microwave mixer theory based on photon-assisted tunneling known as the "Tucker Theory" (1975-85). New phenomena predicted by this theory permit noiseless amplification of incoming signals during heterodyne down-conversion, a process that was previously thought impossible for resistive mixers. This discovery revolutionized millimeter and submillimeter astronomy through development of superconductor-insulator-superconductor (SIS) tunnel junction receivers operating at or near the fundamental limit for sensitivity set by the Heisenberg uncertainty principle. Receivers of this type are currently installed on all major (sub)millimeter astronomical telescopes at high altitude. Due to their extraordinary success, the US and European Community are now constructing one of the world's largest scientific instrument--a 64-element array of 12 meter telescopes with movable platforms on the 5,000m Atacama plain in Chile, each with 6 to 9 dual-polarized SIS receivers to cover the entire spectrum from 84 to 950 GHz at a total cost in excess of $1.3B. By completion in 2013, this Altacama Large Millimeter Array (ALMA) will be the primary instrument for studies of the early universe, planetary and star formation, surveys of molecules in space, the origins of life, and much more for the remainder of this century. Also in 2009, the Herschel Space Telescope will be launched carrying a suite of submillimeter SIS receivers into space for the first time, along with two other modules for the far IR.
  • Initiated atom-scale STM e-beam lithography based on selective desorption of hydrogen from H-passivated Si surfaces in ultra-high vacuum, with Dr. T.-C. Shen (1992-98). We then developed a planar dopant patterning process based on selective adsorption of individual phosphine molecules and self-ordered arrays onto STM-exposed Si dangling bonds, followed by low-temperature Si overgrowth to incoporate the P atoms into the crystal lattice as activated donors (1998-2002). Wavefunctions of bound-state electrons orbiting these donors can be configured into atom-scale circuits encapsulated in silicon, eliminating all surface effects and random influences. The first such devices were demonstrated in 2003 by our group, and by the Australian Research Center for Quantum Computer Technology in Sydney. Our multi-investigator UIUC Center for Silicon Quantum Computers was a leading institution, along with the Australian Centre, in the effort to build a silicon-based quantum computer(2001-2005). Since 2005, my research has been focused on building 3D epitaxial integrated circuits based on merging our selective delta-doping process with Si/SiGe heterolayers. A patent on these ideas combined with UV excimer lithography was filed January 18, 2006. Recently in 2008, I have drawn up a new ultra-low-power architecture with a density of ~1 billion gates/cm2.
  • Proposed gate-induced tunneling (field emission) as a new principle for metal silicide source/drain MOS transistors that permit scaling to sub-25nm gate length without impurity doping or non-planar architecture (1994). PtSi devices with good current drive were fabricated by my UIUC graduate student Chinlee Wang at 27nm gate length under DARPA sponsorship (1997). Based on our results, a UC Berkeley team lead by Chenming Hu and Jeff Bokor reported both p-type PtSi and n-type ErSi2 devices at ~20nmx25nm overall dimensions on ultra-thin SOI substrates, showing 105 turn-off at room temperature. These results upstaged Intel's 30nm devices in most of the publicity at IEDM 2000. These devices remain among the smallest MOS transistors in overall dimension, and potentially the fastest CMOS technology. Two start-up companies worked in the U.S. to develop this approach to 'ultimate scaling', along with parallel research in the Far East. A new high-frequency world record for a MOS transistor was established in 2004 with p-type silicide source/drain devices fabricated by MIT Lincoln Laboratory. In 2005, an International Symposium on Metal Source/Drain Technology was organized at Stanford. Over the next two years, Intel made the future decision to approach the scaling limit with a non-planar FinFet (Tri-Gate) architecture. Thus far, conventional 2D Si FETs now have metal gates and a high-k dielectric. With those two improvements, a 2D metal silicide source/drain architecture may yet prevail due to the very large reductions in parasitics--and the ability to drain the deposited energy much faster from the silicide drain.
  • Chairman, MicroDevices Laboratory Visiting Committee, Jet Propulsion Laboratory, NASA/Caltech, 2008-
  • Review Panel, Laboratory Directed Research and Development Programs, Los Alamos National Laboratory, May 2001 and 2002.